Power Quality Aggregator Module
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Overview
The Power Quality Aggregator module has pulse outputs for the IEC 61000-4-30 Class A compliance (“4-30”) intervals (150/180 cycles, 10 seconds, 10 minutes and 2 hours).
The Power Quality Aggregator module complies with the following sections of the IEC 61000-4-30 standard:
- r.m.s. voltage refreshed each half-cycle, Urms (1/2)
- Measurement aggregation over time intervals
- Measurement aggregation algorithm
- Power frequency
- Magnitude of the supply voltage
- Calculation of a sliding reference voltage
- Underdeviation and overdeviation
- Magnitude of current
For more information on IEC 61000-4-30 implementation in ION meters, refer to the IEC 61000-4-30 Compliance and ION meters technical note.
Inputs
The Power Quality Aggregator module has the following inputs:
These registers are linked to the Vln a, Vln b, and Vln c outputs of the High Speed Power Meter module and cannot be changed.
These registers are linked to the Vll ab, Vll bc, and Vll ca outputs of the High Speed Power Meter module and cannot be changed.
This register reflects the power system's configuration. This register is linked to the Volts Mode setup register on the High Speed Power Meter module and cannot be changed. The VoltsMode determines which High Speed Power Meter module outputs (line-to-neutral or line-to-line) are used to calculate the outputs of the Power Quality Aggregator module. The table below shows what Power Quality Aggregator inputs are used for the 3 voltage aggregates based on the different VoltsMode settings.
VoltsMode register setting | Input link to High-Speed Power Meter | ||
---|---|---|---|
V1 aggregate | V2 aggregate | V3 aggregate | |
4W-Wye or 9S ‑ 4 Wire Wye/Delta | V LN1 to Vln a | V LN2 to Vln b | V LN3 to Vln c |
3W-Wye or 29S ‑ 4 Wire Wye or 36S ‑ 4 Wire Wye | V LN1 to Vln a | V LN2 to Vln b | V LN3 to Vln c |
Delta or 35S ‑ 3 Wire | V LL12 to Vll ab | V LL23 to Vll bc | V LL31 to Vll ca |
Single | V LN1 to Vln a | V LN2 to Vln b | N/A |
Demo | N/A | N/A | N/A |
Line-to-line (LL) values are used for systems that do not have a neutral. Line-to-neutral (LN) values are used for systems with a neutral. You can override this behavior with the Volts Method setup register.
This register specifies the nominal voltage of the power system.
These registers are linked to the High Speed Power Meter module’s I a, I b and I c outputs respectively and cannot be changed.
This register is linked to the NomFreq setup register of the Factory module and cannot be changed.
This register enables or disables the module. Linking this input is optional; if you leave it unlinked, the module is enabled by default.
Setup registers
This register determines the input values used by the Power Quality Aggregator module. When volts mode v ll is selected, the module uses the VLL inputs to calculate all V outputs with an unstated configuration. In automatic - pm volts mode dependent, the module uses either V1, V2 and V3 inputs or the V1 Delta, V2 Delta and V3 Delta inputs for its calculations, based on the Volts Mode setting in the Power Meter module. Any VLL or VLN labeled outputs are unaffected.
Output registers
The Power Quality Aggregator module contains the following output registers:
V1 150 180 Cycle (V1 3s), V2 150 180 Cycle (V2 3s), and V3
150 180 Cycle (V3 3s)
These registers are the 150/180 cycle measurements for magnitude of supply voltage as described in 4-30 section 4.4. The output values are updated at the completion of each 150/180 cycle interval.
I1 150 180 Cycle (I1 3s), I2 150 180 Cycle (I2 3s), and I3
150 180 Cycle (I3 3s)
These registers are used in the 150/180 cycle measurement for current, as described in 4-30 section 4.4. The output values are updated at the completion of each 150/180 cycle interval.
V1, V2 and V3 OverDev 150 180 Cycles
These registers are the overdeviation 150/180 cycle aggregates based on the 10/12 cycle overdeviation aggregates, as described in 4-30 section 5.12. The output values are updated at the completion of each 150/180 cycle interval.
V1, V2 and V3 UnderDev 150 180 Cycles
These registers are the underdeviation calculations based on the 10/12 cycle underdeviation aggregates, as described in 4-30 section 5.12. The output values are updated at the completion of each 150/180 cycle interval.
This register is pulsed at the end of 150/180 cycle intervals.
V1 10 Minute, V2 10 Minute, and V3 10 Minute
These registers are the 10 minute interval aggregates of the basic measurement intervals (10/12-cycle) described in 4-30 section 4.4. The values are updated every 10 minutes.
I1 10 Minute, I2 10 Minute, and I3 10 Minute
These registers are the 10 minute interval aggregates of the basic measurement intervals (10/12-cycle) described in 4-30 section 4.4. The values are updated every 10 minutes.
V1, V2 and V3 OverDev 10 Minute
These registers are the overdeviation calculations based on the 10 minute Vrms as described in 4-30 section 5.12. The values are updated every 10 minutes.
V1, V2 and V3 UnderDev 10 Minute
These registers are the underdeviation calculations based on the 10 minute Vrms as described in 4-30 section 5.12. The values are updated every 10 minutes.
This register is pulsed at the end of every 10 minute aggregation interval.
This register is pulsed at the end of every 2 hour aggregation interval.
This register is the ratio of the number of integral cycles counted during a 10 second clock interval, divided by the cumulative duration of the integer cycles. Individual cycles that overlap the 10 second boundary are discarded from the measurement as defined in 4-30 section 5.1.
This numeric register is the internal channel number where frequency is being measured.
This register is pulsed when the Power Frequency has been updated, pulsed at approximately 10 second intervals synchronized to the clock.
VLN1 Half-Cycle, VLN2 Half-Cycle, VLN3 Half-Cycle
These registers are the LN rms voltages measured over 1 cycle, commencing at a fundamental zero crossing, and refreshed every half-cycle as defined in 4-30 section 3.24.
VLL12 Half-Cycle, VLL23 Half-Cycle, VLL31 Half-Cycle
These are the L-L rms voltages measured over 1 cycle, commencing at a fundamental zero crossing, and refreshed every half-cycle as defined in 4-30 section 3.24.
This is calculated using the aggregate of V L1-N or V L1-L2, depending on the VoltsMode, as defined in 4-30 section 5.4.4.
This register contains the sliding reference voltage for V1, as defined in 4-30 section 5.4.4.
This register contains the sliding reference voltage for V2, as defined in 4-30 section 5.4.4.
This register contains the sliding reference voltage for V3, as defined in 4-30 section 5.4.4.
This register contains the average sliding reference voltage for all three phases (V1, V2 and V3), as defined in 4-30 section 5.4.4.
All events are recorded in the Event register. Possible events and their associated priority numbers are:
Event priority group | Priority | Description |
---|---|---|
Setup Change | 10 | Input links, setup registers or labels have been changed |
The Event output register stores the following information for each ION event: time stamp, priority, cause, effect, and any values or conditions associated with the cause and effect.