Cyclic Data Description

Introduction

The tables below describe the different cyclic data types in byte format and word format (little endian and big endian):

Status: input data
Command: output data
PKW IN: input data (available only in word format)
PKW OUT: output data (available only in word format)

Cyclic Data in Byte Format

Cyclic data types in byte format are:

Status: input data
Command: output data

Status input data in byte format: Input 0 to Input 9

Position	Description
Input 0.0 Run Reverse	The main circuit contacts are closed.
Input 0.1 Off	Indication that the device is in the OFF state.
Input 0.2 Run Forward	The main circuit contacts are closed.
Input 0.3 Thermal Overload Alarm	An overload alarm condition exists. (461.3)
Input 0.4 Lockout Time	Communication status register high byte (456.4)
Input 0.5 Auto Mode	Indication to a remote host controller that the RUN FORWARD, RUN REVERSE and STOP commands will or will not be accepted. 0 = LOCAL CONTROL 1 = AUTO MODE
Input 0.6 System Trip	A trip condition exists. (455.2)
Input 0.7 System Alarm	An alarm condition exists. (455.3)
Input 1.0 to 1.3 Reserved	Reserved
Input 1.4 System Ready	Ready (455.0)
Input 1.5 Motor Ramping	Motor ramping: start in progress (455.15)
Input 1.6 Motor Running	Motor running: current > 20% FLC Min (455.7)
Input 1.7 System tripped	System tripped (455.4)
Input 2	Iav average current - MSB
Input 3	Iav average current - LSB
Input 4 Logic Inputs 9-16 of expansion module	Logic inputs status High byte (457.8-15)
Input 5 Logic Inputs 1-6 of LTMR controller + inputs 7-8 of expansion module	Logic inputs status Low byte (457.0-7)
Input 6 Reserved	Logic outputs status High byte (458.8-9) (458.10-15 are not significant)
Input 7 Status of logic outputs 13, 23, 33, and 95	Logic outputs status Low byte (458.0-3) (458.4-7 are not significant)
Input 8 (456.8) Network port comm loss (456.9) Motor lockout (456.10-15) Reserved	System status register 2 High byte (456.8-15)
Input 9 (456.0) Auto reset active (456.1) Reserved (456.2) Controller power cycle requested (456.3) Motor restart time undefined (456.4) Rapid cycle lockout (456.5) Load shedding (456.6) Motor high speed (456.7) HMI port comm loss	System status register 2 Low byte (456.0-7)

Position

Description

Input 0.0

Run Reverse

The main circuit contacts are closed.

Input 0.1

Off

Indication that the device is in the OFF state.

Input 0.2

Run Forward

The main circuit contacts are closed.

Input 0.3

Thermal Overload Alarm

An overload alarm condition exists.

(461.3)

Input 0.4

Lockout Time

Communication status register high byte (456.4)

Input 0.5

Auto Mode

Indication to a remote host controller that the RUN FORWARD, RUN REVERSE and STOP commands will or will not be accepted.

0 = LOCAL CONTROL

1 = AUTO MODE

Input 0.6

System Trip

A trip condition exists.

(455.2)

Input 0.7

System Alarm

An alarm condition exists.

(455.3)

Input 1.0 to 1.3

Reserved

Input 1.4

System Ready

Ready

(455.0)

Input 1.5

Motor Ramping

Motor ramping: start in progress

(455.15)

Input 1.6

Motor Running

Motor running: current > 20% FLC Min

(455.7)

Input 1.7

System tripped

(455.4)

Input 2

Iav average current - MSB

Input 3

Iav average current - LSB

Input 4

Logic Inputs 9-16 of expansion module

Logic inputs status

High byte

(457.8-15)

Input 5

Logic Inputs 1-6 of LTMR controller + inputs 7-8 of expansion module

Logic inputs status

Low byte

(457.0-7)

Input 6

Reserved

Logic outputs status

High byte

(458.8-9)

(458.10-15 are not significant)

Input 7

Status of logic outputs 13, 23, 33, and 95

Logic outputs status

Low byte

(458.0-3)

(458.4-7 are not significant)

Input 8

(456.8) Network port comm loss

(456.9) Motor lockout

(456.10-15) Reserved

System status register 2

High byte

(456.8-15)

Input 9

(456.0) Auto reset active

(456.1) Reserved

(456.2) Controller power cycle requested

(456.3) Motor restart time undefined

(456.4) Rapid cycle lockout

(456.5) Load shedding

(456.6) Motor high speed

(456.7) HMI port comm loss

System status register 2

Low byte

(456.0-7)

Command output data in byte format: Output 0 to Output 5

Position	Description
Output 0.0 Run Reverse	Instructs the starter to energize the motor in the reverse direction.
Output 0.1 Off	Instructs the device to go to the OFF state. 0 = ENABLE RUN FORWARD/ RUN REVERSE 1 = OFF
Output 0.2 Run Forward	Instructs the starter to energize the motor in the forward direction.
Output 0.3 Self Test Command	Instructs the device to initiate an internal test routine within the device. (704.5)
Output 0.4 Clear Thermal Capacity Level Command	Reset thermal memory Instructs the starter to override any trip condition and allows starting. (705.2) Note: This command inhibits thermal protection. Continued operation with inhibited thermal protection should be limited to applications where immediate restart is vital. By setting this bit to 1, the thermal state of the motor is lost: the thermal protection will no longer protect an already warm motor.
Output 0.5 Reserved	Reserved
Output 0.6 Trip Reset Command	Trip reset Instructs the starter to reset all resettable trips (one of the preconditions for READY). (704.3)
Output 0.7 Reserved	Reserved
Output 1.0 to 1.4 Reserved	Reserved
Output 1.5 Motor Low Speed Command	Low speed (704.6)
Output 1.6 to 1.7 Reserved	Reserved
Output 2 Additional Output	Analog output (to manage by custom logic, future extension) (706.8-15)
Output 3 Additional Output	Analog output (to manage by custom logic, future extension) (706.0-7)
Output 4 Additional Output	Logic outputs command register High byte (700.8-15: Reserved)
Output 5 Additional Output	Logic outputs command register Low byte (700.0-3: associated to Output 1 to 4 if custom logic manages it) (700.4-15: Reserved)

Position

Description

Output 0.0

Run Reverse

Instructs the starter to energize the motor in the reverse direction.

Output 0.1

Off

Instructs the device to go to the OFF state.

0 = ENABLE RUN FORWARD/ RUN REVERSE

1 = OFF

Output 0.2

Run Forward

Instructs the starter to energize the motor in the forward direction.

Output 0.3

Self Test Command

Instructs the device to initiate an internal test routine within the device.

(704.5)

Output 0.4

Clear Thermal Capacity Level Command

Reset thermal memory

Instructs the starter to override any trip condition and allows starting.

(705.2)

Note: This command inhibits thermal protection. Continued operation with inhibited thermal protection should be limited to applications where immediate restart is vital. By setting this bit to 1, the thermal state of the motor is lost: the thermal protection will no longer protect an already warm motor.

Output 0.5

Reserved

Output 0.6

Trip Reset Command

Trip reset

Instructs the starter to reset all resettable trips (one of the preconditions for READY).

(704.3)

Output 0.7

Reserved

Output 1.0 to 1.4

Reserved

Output 1.5

Motor Low Speed Command

Low speed (704.6)

Output 1.6 to 1.7

Reserved

Output 2

Additional Output

Analog output (to manage by custom logic, future extension)

(706.8-15)

Output 3

Additional Output

Analog output (to manage by custom logic, future extension)

(706.0-7)

Output 4

Additional Output

Logic outputs command register

High byte

(700.8-15: Reserved)

Output 5

Additional Output

Logic outputs command register

Low byte

(700.0-3: associated to Output 1 to 4 if custom logic manages it)

(700.4-15: Reserved)

Cyclic Data in Word Little Endian Format

Cyclic data types in Word little endian format are:

Status: input data
PKW IN: input data
Command: output data
PKW OUT: output data

Status input data in word little endian format: IW 0 to IW 4

Word Arrangement				Byte N°
IW 0	MSB	bit 15	System tripped (455.4)	Input 1
		bit 14	Motor running (455.7)
		bit 13	Motor starting (455.15)
		bit 12	System ready (455.0)
		bit 8 to bit 11	Reserved
	LSB	bit 7	System alarm (455.3)	Input 0
		bit 6	System trip (455.2)
		bit 5	Auto mode
		bit 4	Lock out time
		bit 3	Thermal overload alarm (461.3)
		bit 2	Run Forward
		bit 1	Off
		bit 0	Run Reverse
IW 1	MSB	bit 8 to bit 15	IAV average current % FLC LSB 466.0 to 466.7	Input 3
IW 1	LSB	bit 0 to bit 7	IAV average current % FLC MSB 466.8 to 466.15	Input 2
IW 2	MSB	bit 8 to bit 15	Logic inputs status LSB 457.0 to 457.7 Inputs 1-6 of controller Inputs 7-8 of expansion module	Input 5
IW 2	LSB	bit 0 to bit 7	Logic inputs status MSB 457.8 to 457.15 Inputs 9-16 of expansion module (11-16 future extension)	Input 4
IW 3	MSB	bit 12 to bit 15	Outputs 5-8 of expansion module (future extension) 458.4 to 458.7	Input 7
		bit 11	Logic output 95 status (458.3)
		bit 10	Logic output 33 status (458.2)
		bit 9	Logic output 23 status (458.1)
		bit 8	Logic output 13 status (458.0)
	LSB	bit 0 to bit 7	Outputs 9-16 of expansion module (future extension) 458.8 to 458.15	Input 6
IW 4	MSB	bit 15	HMI port comm loss (456.7)	Input 9
		bit 14	Motor high speed (456.6)
		bit 13	Load shedding (456.5)
		bit 12	Rapid cycle lockout (456.4)
		bit 11	Motor restart time undefined (456.3)
		bit 10	Controller power cycle requested (456.2)
		bit 9	Reserved (456.1)
		bit 8	Auto reset active (456.0)
	LSB	bit 2 to bit 7	Reserved (456.10 to 456.15)	Input 8
		bit 1	Motor transition lockout (456.9)
		bit 0	Network port comm loss (456.8)

PKW IN input data in word little endian format: IW 5 to IW 8 (supported by modules with PKW)

Word Arrangement
IW 5	MSB	bit 8 to bit 15	Object address MSB
IW 5	LSB	bit 0 to bit 7	Object address LSB
IW 6	MSB	bit 15	Toggle bit
	MSB	bit 8 to bit 14	Function
	LSB	bit 0 to bit 7	Not used: 0x00
IW 7	MSB	bit 8 to bit 15	Data read in register 1 MSB
IW 7	LSB	bit 0 to bit 7	Data read in register 1 LSB
IW 8	MSB	bit 8 to bit 15	Data read in register 2 MSB
IW 8	LSB	bit 0 to bit 7	Data read in register 2 LSB

Command output data in word little endian format: QW 0 to QW 2

Word Arrangement				Byte N°
QW 0	MSB	bit 14 to bit 15	Reserved	Output 1
		bit 13	Motor low speed command (704.6)
		bit 8 to bit 12	Reserved
	LSB	bit 7	Reserved	Output 0
		bit 6	Trip reset command
		bit 5	Auto mode
		bit 4	Clear thermal capacity level command (705.2)
		bit 3	Self test command (704.5)
		bit 2	Run Forward (704.0)
		bit 1	OFF
		bit 0	Run Reverse (704.1)
QW 1	MSB	bit 8 to bit 15	Analog output LSB (future extension) 706.0 to 7	Output 3
QW 1	LSB	bit 0 to bit 7	Analog output MSB (future extension) 706.8 to 15	Output 2
QW 2	MSB	bit 9 to bit 15	Logic output command register LSB 700.4 to 7 Outputs 5 to 8 (future extension)	Output 5
	MSB	bit 8 to 11	Logic output command register LSB 700.0 to 3 Outputs 1 to 4 (13, 23, 33, 95) if custom logic manages it	Output 5
	LSB	bit 0 to bit 7	Logic output command register MSB 700.8 to 15 Outputs 9 to 16 (future extension)	Output 4

PKW OUT output data in word little endian format: QW 3 to QW 6 (supported by modules with PKW)

Word Arrangement
QW 3	MSB	bit 8 to bit 15	Object address MSB
QW 3	LSB	bit 0 to bit 7	Object address LSB
QW 4	MSB	bit 15	Toggle bit
	MSB	bit 8 to bit 14	Function
	LSB	bit 0 to bit 7	Not used: 0x00
QW 5	MSB	bit 8 to bit 15	Data write in register 1 MSB
QW 5	LSB	bit 0 to bit 7	Data write in register 1 LSB
QW 6	MSB	bit 8 to bit 15	Data write in register 2 MSB
QW 6	LSB	bit 0 to bit 7	Data write in register 2 LSB

Cyclic Data in Word Big Endian Format

Cyclic data types in Word big endian format are:

Status: input data
PKW IN: input data
Command: output data
PKW OUT: output data

Status input data in word big endian format: IW 0 to IW 4

Word Arrangement				Byte N°
IW 0	MSB	bit 15	System alarm (455.3)	Input 0
		bit 14	System trip (455.2)
		bit 13	Auto mode
		bit 12	Lock out time
		bit 11	Thermal overload alarm (461.3)
		bit 10	Run Forward
		bit 9	OFF
		bit 8	Run Reverse
	LSB	bit 7	System tripped (455.4)	Input 1
		bit 6	Motor running (455.7)
		bit 5	Motor ramping (455.15)
		bit 4	System ready (455.0)
		bit 0 to 3	Reserved
IW 1	MSB	bit 8 to bit 15	IAV average current % FLC MSB 466.8 to 466.15	Input 2
IW 1	LSB	bit 0 to bit 7	IAV average current % FLC LSB 466.0 to 466.7	Input 3
IW 2	MSB	bit 8 to bit 15	Logic input status MSB 457.8 to 15 Inputs 9-16 of expansion module (11-16 future extension)	Input 4
IW 2	LSB	bit 0 to bit 7	Logic input status LSB 457.0 to 457.7 Inputs 1-6 of controller Inputs 7-8 of expansion module	Input 5
IW 3	MSB	bit 8 to bit 15	Outputs 9-16 of expansion module (future extension) 458.8 to 458.15	Input 6
	LSB	bit 4 to bit 7	Outputs 5-8 of expansion module (future extension) 458.4 to 458.7	Input 7
		bit 3	Logic output 95 status (458.3)
		bit 2	Logic output 33 status (458.2)
		bit 1	Logic output 23 status (458.1)
		bit 0	Logic output 13 status (458.0)
IW 4	MSB	bit 10 to bit 15	Reserved (456.10 to 456.15)	Input 8
		bit 9	Motor transition lockout (456.9)
		bit 8	Network port comm loss (456.8)
	LSB	bit 7	HMI port comm loss (456.7)	Input 9
		bit 6	Motor high speed (456.6)
		bit 5	Load shedding (456.5)
		bit 4	Rapid cycle lockout (456.4)
		bit 3	Motor restart time undefined (456.3)
		bit 2	Controller power cycle requested (456.2)
		bit 1	Reserved (456.1)
		bit 0	Auto reset active (456.0)

PKW IN input data in word big endian format: IW 5 to IW 8 (supported by modules with PKW)

Word Arrangement
IW 5	MSB	bit 8 to bit 15	Object address LSB
IW 5	LSB	bit 0 to bit 7	Object address MSB
IW 6	MSB	bit 8 to bit 15	Not used: 0x00
	LSB	bit 7	Toggle bit
	LSB	bit 0 to bit 6	Function
IW 7	MSB	bit 8 to bit 15	Data read in register 1 LSB
IW 7	LSB	bit 0 to bit 7	Data read in register 1 MSB
IW 8	MSB	bit 8 to bit 15	Data read in register 2 LSB
IW 8	LSB	bit 0 to bit 7	Data read in register 2 MSB

Command output data in word big endian format: QW 0 to QW 2

Word Arrangement				Byte N°
QW 0	MSB	bit 15	Reserved	Output 0
		bit 14	Trip reset command
		bit 13	Auto mode
		bit 12	Clear thermal capacity level command (705.2)
		bit 11	Self test command (704.5)
		bit 10	Run Forward (704.0)
		bit 9	OFF
		bit 8	Run Reverse (704.1)
	LSB	bit 6 to bit 7	Reserved	Output 1
		bit 5	Motor low speed command (704.6)
		bit 0 to bit 4	Reserved
QW 1	MSB	bit 8 to bit 15	Analog output MSB (future extension) 706.8 to 15	Output 2
QW 1	LSB	bit 0 to bit 7	Analog output LSB (future extension) 706.0 to 7	Output 3
QW 2	MSB	bit 8 to bit 15	Logic output command register MSB 700.8 to 15 Outputs 9 to 16 (future extension)	Output 4
	LSB	bit 4 to bit 7	Logic output command register LSB 700.4 to 7 Outputs 5 to 8 (future extension)	Output 5
	LSB	bit 0 to 3	Logic output command register LSB 700.0 to 3 Outputs 1 to 4 (13, 23, 33, 95) if custom logic manages it	Output 5

PKW OUT output data in word big endian format: QW 3 to QW 6 (supported by modules with PKW)

Word Arrangement
QW 3	MSB	bit 8 to bit 15	Object address LSB
QW 3	LSB	bit 0 to bit 7	Object address MSB
QW 4	MSB	bit 8 to bit 15	Not used: 0x00
	LSB	bit 7	Toggle bit
	LSB	bit 0 to bit 6	Function
QW 5	MSB	bit 8 to bit 15	Data write in register 1 LSB
QW 5	LSB	bit 0 to bit 7	Data write in register 1 MSB
QW 6	MSB	bit 8 to bit 15	Data write in register 2 LSB
QW 6	LSB	bit 0 to bit 7	Data write in register 2 MSB