Digital Input Interlock Protection Settings

Description

Each digital input interlock protection settings are made up of five registers. The order and the description of the settings for digital input 1 interlock are valid for the other digital inputs.

Address	Register	RW	Function code	Description
0x0F23–0x0F27	3876–3880	RW	0x03,0x06,0x10	Digital input 1 interlock protection settings
0x0F28–0x0F2C	3881–3885	RW	0x03,0x06,0x10	Digital input 2 interlock protection settings
0x0F2D–0x0F31	3886–3890	RW	0x03,0x06,0x10	Digital input 3 interlock protection settings
0x0F32–0x0F36	3891–3895	RW	0x03,0x06,0x10	Digital input 4 interlock protection settings
0x0F37–0x0F3B	3896–3900	RW	0x03,0x06,0x10	Digital input 5 interlock protection settings
0x0F3C–0x0F40	3901–3905	RW	0x03,0x06,0x10	Digital input 6 interlock protection settings
0x0F41–0x0F45	3906–3910	RW	0x03,0x06,0x10	Digital input 7 interlock protection settings
0x0F46–0x0F4A	3911–3915	RW	0x03,0x06,0x10	Digital input 8 interlock protection settings
0x0F4B–0x0F4F	3916–3920	RW	0x03,0x06,0x10	Digital input 9 interlock protection settings
0x0F50–0x0F54	3921–3925	RW	0x03,0x06,0x10	Digital input 10 interlock protection settings
0x0F55–0x0F59	3926–3930	RW	0x03,0x06,0x10	Digital input 11 interlock protection settings
0x0F5A–0x0F5E	3931–3935	RW	0x03,0x06,0x10	Digital input 12 interlock protection settings

Digital Input 1 Interlock Protection Settings

The table lists the registers for the digital input interlock protection settings.

Address	Register	No.	Function code	RW	X	Unit	Type	Range	Default value	Svd	Description
0x0F23	3876	1	0x03, 0x06, 0x10	RW	1	–	UINT16	0: Disable 1: Alarm 2: Trip 3: Alarm and Trip	0	Y	Function setting
0x0F24	3877	1	0x03, 0x06, 0x10	RW	0.1	s	UINT16	0–6000 (step 1)	0	Y	Time delay
0x0F25	3878	1	0x03, 0x06, 0x10	RW	1	–	BITMAP	Bit 0: Reset key Bit 1: DI Bit 2: Communication Bit 3: Auto	3	Y	Reset mode
0x0F26	3879	1	0x03, 0x06, 0x10	RW	0.1	s	UINT16	0–6000 (step 1)	0	Y	Auto-Reset delay
0x0F27	3880	1	–	–	–	–	–	–	–	–	Reserved