DOCA0258EN-00

Analog Input Protection Settings

Description

The TeSys Tera system supports up to four analog inputs with two LTMTAN21 expansion modules.

Each analog input protection settings are made up of eight registers. The order and the description of the settings for analog input 1 are valid for the other analog inputs.

Modbus TCP/IP Address (Register)

EtherNet/IP Address

RW

Description

0x0FA0–0x0FA7 (4001–4008)

84 : 02 : 01 – 84 : 02 : 08

RW

Analog input 1 protection settings

0x0FA8–0x0FAF (4009–4016)

84 : 02 : 09 – 84 : 02 : 16

RW

Analog input 2 protection settings

0x0FB0–0x0FB7 (4017-4024)

84 : 02 : 17 – 84 : 02 : 24

RW

Analog input 3 protection settings

0x0FB8–0x0FBF (4025–4032)

84 : 02 : 25 – 84 : 02 : 32

RW

Analog input 4 protection settings

Analog Input 1 Protection Settings

The table lists the registers for the analog input protection settings.

Modbus TCP/IP Address (Register)

EtherNet/IP Address

RW

X

Unit

Type

Range

Default value

Svd

Description

0x0FA0 (4001)

84 : 02 : 01

RW

1

UINT16

  • 0: Disable

  • 1: Alarm
  • 2: Trip
  • 3: Alarm and Trip

0

Y

Function setting

0x0FA1 (4002)

84 : 02 : 02

RW

1

UINT16

  • 0: Under

  • 1: Over

0

Y

Detection

0x0FA2 (4003)

84 : 02 : 03

RW

0.1

mA

UINT16

40–200
(step 1)

40

Y

Pickup

0x0FA3 (4004)

84 : 02 : 04

RW

0.1

s

UINT16

0–60000
(step 1)

0

Y

Time delay

0x0FA4 (4005)

84 : 02 : 05

RW

0.1

mA

UINT16

40–200
(step 1)

40

Y

Alarm

0x0FA5 (4006)

84 : 02 : 06

RW

1

BITMAP

  • Bit 0: Reset key

  • Bit 1: DI
  • Bit 2: Communication
  • Bit 3: Auto

3

Y

Reset mode

0x0FA6 (4007)

84 : 02 : 07

RW

0.1

s

UINT16

0–60000
(step 1)

0

Y

Auto-Reset delay

0x0FA7 (4008)

84 : 02 : 08

RW

1

UINT16

  • 0: Disable

  • 1: Enable

0

Y

Diagnostic

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